1. Field of the Invention
The present invention relates to a modular multiplication device used for technique of information security, and more particularly, to a modular multiplication device for information security which needs only the hardware almost half as much as required in a conventional modular multiplication device wherein multiplication and division circuits are separately used, by performing a dual function of multiplication and division with a binary adder.
2. Description of the Related Art
Recently, the implementation of the hardware directed to an information security algorithm with one chip has become a major issue. Particularly, the secrecy level of algorithms tends to be stressed in an attempt to enhance the function of information security as a result of the advance of the cryptanalysis technology. In order to enhance a secrecy level, it is becoming generalized to design algorithms by using a modular exponentiation calculation with a large amount of calculations. Since the calculation of a modular exponentiation consists of many modular multiplications, the implementation of a modular multiplication for enhancing the processing speed of an information security algorithm is becoming important. The modular multiplication needs a division function as well as a general multiplication function. With the conventional technique for implementing a modular multiplication, the required hardware was implemented so as to perform a modular multiplication function by combining the conventional multiplication and division circuits. According to this implementation method, the problem arises that an one-chip implementation is not viable because the hardware for implementing the information security algorithm with a key having a large amount of bits becomes bulky.
The conventional technique has been using a multiplication circuit for multiplying a multiplicand and a multiplier, and a division circuit for obtaining a modular value. This kind of multiplication method increases the amount of hardware. Thus, the amount of hardware is becoming large in applications such as an information security technique with the key having a large amount of bits. Further, since a costly semiconductor fabrication process, which results a high integration density, must be used to implement with one chip, the cost required for manufacturing is expensive. The reliability is degraded due to the parasitic effect of the narrow-Channel process in implementing a large number of circuits on one chip.